This invention relates to methods for fabricating integrated circuit chips; and more particularly it relates to such methods whereby crosstalk voltages, which are coupled into a victim net on the chip by multiple adjacent aggressor nets, are within an allowable noise margin.
Conventionally, an integrated circuit chip is comprised of a thin, flat semiconductor substrate which is rectangular in shape and is about one-half inch on a side. Integrated into one surface of that substrate are a huge number of microscopic transistors; and on top of those transistors, several patterned layers of conductive material and several patterned layers of insulating material are fabricated in a stack. These insulating layers and conductive layers alternate such that any two conductive layers are separated by an insulating layer. Typically, the insulating layers are made of silicon dioxide, and the conductive layers are made of metal or doped polysilicon.
All of the conductive layers are patterned to form signal lines which interconnect the transistors, and they are also patterned to form DC voltage busses and ground busses by which power is supplied to the transistors. Some of the signal lines interconnect the transistors into multiple logic gates, such as AND gates, OR gates, NAND gates, etc.; and the remaining signal lines intercouple the logic gates to each other to thereby perform some predetermined logic function.
With present day technology, the typical number of transistors on a single chip is about one million; the typical number of logic gates which are formed by the transistors is about 150,000; and the typical number of signal lines which interconnect the logic gates is about 40,000. Each such interconnection from the output from one logic gate (the driver) to the input of one or more other logic gates (the receivers) is herein called a "net".
Ideally, the digital signals which are generated by a driver logic gate on one particular net will not affect the digital signals which are generated by any other driver logic gate on any other net. However, whenever two nets have signal line segments which lie next to each other, then a distributed parasitic capacitance will exist between them; and consequently, a voltage transition on one signal line (herein called an aggressor net) will cause a certain amount of crosstalk voltage to be coupled into the other signal line (herein called a victim net).
As long as the magnitude of the crosstalk voltage is only a small percentage of the voltage swing V.sub.S from a "0" and a "1" logic level, then the crosstalk voltage will not cause the chip to malfunction. However, if the crosstalk voltage exceeds approximately 25%-35% of the voltage swing V.sub.S, then a malfunction on the chip can occur. Specifically, when a driver logic gate in a victim net is generating a "0", the total crosstalk voltage from all adjacent aggressor nets can temporarily cause that "0" to be interpreted as a "1" by a receiving logic gate. Likewise, when a driver logic gate in a victim net is generating a "1", the total crosstalk voltage from all adjacent aggressor nets can temporarily cause that "1" to be interpreted as a "0" by a receiving logic gate.
To avoid the above problem, it is desirable to be able to predict before a chip is built, the respective magnitudes of the crosstalk voltages which will be coupled into the victim nets on a chip by all of the adjacent aggressor nets. In the prior art, this could be attempted through a SPICE simulation of a proposed layout for each victim net and all of the adjacent aggressor nets. SPICE is a computer program which simulates electrical circuits; and it is available from the University of California at Berkeley, via the Department of Electrical Engineering and Computer Sciences. However, a SPICE simulation of all the nets in an entire chip is far too complex to be practical.
In order to perform a SPICE simulation of a circuit, all of the nodes between every component in the circuit need to be numbered. Then those nodes, the type of components at each node, and the component magnitudes are entered into the SPICE program.
If the circuit which is being simulated is an entire integrated circuit chip, then the number of nodes and corresponding components which need to be entered into the SPICE program is overwhelming. Firstly, the number of nets is about 40,000. Secondly, for each such net, about seventy discreet components need to be entered because in the actual chip, the net components are distributed. Specifically, each signal line has capacitance which is distributed throughout the line; and each signal line also has a resistance which is distributed throughout the line. To simulate these distributed components, each signal line needs to be represented by a ladder circuit which has about two dozen nodes; with each node having a resistor to the next node, a capacitor to ground, and a capacitor to any adjacent signal line.
After all of the nodes and corresponding components for all the nets are entered into the SPICE program, the program operates to determine the voltages which occur on each node in sequential increments of time. Typically, about 1,000 increments of ten picoseconds each are needed to obtain the entire voltage waveform on a node in one net in an integrated circuit chip. To determine the voltages for just one time increment, the SPICE program repetitively solves a matrix equation which is of the form [Y][V]=[I]. Here, Y is an n.times.n matrix, V is an n.times.1 matrix, and I is an n.times.1 matrix; where n is the number of nodes in the circuit. Thus, for a single victim net with twenty aggressor nets, n is (24 nodes per net).times.(21 nets) or 504.
For each increment in time, the SPICE program makes about five iterations before it converges on a solution. This iterative process is repeated for each of the subsequent time increments.
Using a state of the art workstation, it takes about ten minutes to perform a SPICE simulation of a single circuit which has 500 nodes and for which a solution is sought for 1,000 time increments. Such a circuit represents a typical victim net with twenty aggressor nets. Consequently, to simulate a chip which has 40,000 nets would take about 400,000 minutes, or more than 270 days to complete!
Accordingly, a primary object of the present invention is to provide a method of fabricating integrated circuit chips by which the above problems are overcome.